Conference
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L. Zhu, N. E. Bethur, Y.-C. Lu, Y. Cho, Y. Im, and S. K. Lim, “3D IC Tier Partitioning of Memory Macros: PPA vs. Thermal Tradeoffs,” in Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, New York, NY, USA, 2022, pp. 1–6. doi: 10.1145/3531437.3539724.
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L. Zhu et al., “Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture,” in 2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Jul. 2021, pp. 1–6. doi: 10.1109/ISLPED52811.2021.9502481. (PDF)
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L. Zhu and S. K. Lim, “Physical Design Challenges and Solutions for Emerging Heterogeneous 3D Integration Technologies,” in Proceedings of the 2021 International Symposium on Physical Design, New York, NY, USA, 2021, pp. 127–134. doi: 10.1145/3439706.3446903. (PDF)
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L. Zhu, K. Chang, D. Petranovic, S. Sinha, Y. S. Yu, and S. K. Lim, “Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs,” in Proceedings of the 2020 International Symposium on Physical Design, New York, NY, USA: Association for Computing Machinery, 2020, pp. 39–46. Accessed: May 18, 2022. [Online]. Available: https://doi.org/10.1145/3372780.3378169 (PDF)
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L. Bamberg, L. Zhu, S. Pentapati, D. E. Shim, A. García-Ortiz, and S. Kyu Lim, “Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs,” in 2020 Design, Automation Test in Europe Conference Exhibition (DATE), Mar. 2020, pp. 37–42. doi: 10.23919/DATE48585.2020.9116297. (PDF)
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L. Zhu, J. Wang, and J. Lai, “Design of a Bit Error Ratio Testing and Error Correction System Based on High-Speed Serial Interface,” in 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct. 2018, pp. 1–3. doi: 10.1109/ICSICT.2018.8564934.
Journal
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L. Zhu, C. Jo, and S. K. Lim, “Power Delivery Solutions and PPA impacts in Micro-Bump and Hybrid Bonding 3D ICs,” IEEE Transactions on Components, Packaging and Manufacturing Technology, pp. 1–1, 2022, doi: 10.1109/TCPMT.2022.3221025.
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L. Zhu et al., “Design Automation and Test Solutions for Monolithic 3D ICs,” J. Emerg. Technol. Comput. Syst., vol. 18, no. 1, pp. 1–49, Jan. 2022, doi: 10.1145/3473462. (PDF)
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L. Zhu et al., “High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors,” IEEE Trans. VLSI Syst., vol. 29, no. 6, pp. 1152–1163, Jun. 2021, doi: 10.1109/TVLSI.2021.3073070. (PDF)
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L. Zhu et al., “Heterogeneous 3D Integration for a RISC-V System With STT-MRAM,” IEEE Computer Architecture Letters, vol. 19, no. 1, pp. 51–54, Jan. 2020, doi: 10.1109/LCA.2020.2992644. (PDF)
